1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a circuit for reducing the clamping voltage in a charge pump for a substrate-bias generator thereby increasing the efficiency and stability of the substrate-bias generator by decreasing the power dissipated by the circuit elements.
2. Discussion of the Prior Art
Recent innovations in N-channel silicon-gate metal-oxide-semiconductor field effect transistor (MOSFETs) processing technology have resulted in very large scale integrated circuits. These high density circuit geometries are so small that MOSFET channel lengths are now comparable to the base widths of bipolar transistors and gate oxides thicknesses have been reduced to below 400 Angstroms. This has opened the way for a generation of N-channel integrated circuits which can operate on supply voltages in the 2-3 V.sub.DC range.
Unfortunately, positive trapped charge that exists in the oxide layer near the surface of the silicon substrate and the positive charge of most undesired ionic contaminants tend to cause N-channel MOSFETs to convert to the depletion mode of operation. For example, in 5V systems, a 0V signal will not turn off an N-channel transistor if it has converted to the depletion mode. This problem was the initial reason for the use of substrate-biasing circuits with N-channel devices, i.e. to control and guarantee a constant threshold voltage.
The use of a negative substrate-bias voltage provides several advantages. It lowers the diffusion-to-substrate capacitance without requiring a decrease in substrate doping. It also protects the device against forward-biasing of diffused PN junctions due to voltage undershoots at the nodes. If feedback is provided, the substrate-bias voltage can also compensate for some device parameter variations.
A description of conventional substrate-bias generating circuitry is provided by Lance A. Glasser and Daniel W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley publishing, pp. 301-308. As described by Glasser and Dobberpuhl, a negative substrate-bias voltage is generated by pumping electrons out of the device's ground node and into the substrate. In most cases, a bond wire connects the V.sub.bb pad to the die bed, making a good contact to the substrate.
An idealized model of a conventional substrate-bias generator is shown in FIG. 1. A driver 10 amplifies an AC input signal generated by an oscillator and powers the charge pump. The power is coupled to the charge pump through capacitor 12. Two diodes, designated D.sub.gnd and D.sub.sub, gate the charge out of the substrate and into the ground node. When the voltage V.sub.pump at node A is near its peak value, then diode D.sub.gnd is forward-biased and charge is pumped into the ground node; at this time, diode D.sub.sub is off. During the other half of the cycle, that is, when voltage V.sub.pump is near its most negative value, diode D.sub.gnd is off while diode D.sub.sub drains charge out of the substrate.
The theoretical minimum value of the substrate-bias voltage V.sub.bb is determined by the peak-to-peak value of V.sub.pump and the voltage drops in the two diodes D.sub.gnd and D.sub.sub. During the high part of the cycle, V.sub.pump must be one diode drop above ground to pump charge. On the low side of the cycle, V.sub.pump must be one diode drop below V.sub.bb to do any work. Assuming the maximum peak-to-peak voltage of V.sub.pump is less than V.sub.dd, then the minimum value of V.sub.bb is greater than or equal to -V.sub.dd +2 diode drops. As shown in FIG. 1, because of leakage currents I.sub.L and parasitic capacitances C.sub.p, such an ideal value is rarely achieved.
Due to constraints imposed by N-channel technology, diode D.sub.gnd is generally implemented as an enhancement-mode transistor 16 with its gate and drain tied together. Diode D.sub.sub may also be implemented as an enhancement mode transistor 14. A charge pump circuit which implements this substitution of transistors 14 and 16 is shown in FIG. 2. As further shown in FIG. 2, capacitor 12 of FIG. 1 is typically implemented as a depletion mode transistor 18 with its source and drain connected together and with its gate connected to receive the output of driver 10.
When the input voltage to the substrate-bias generator circuit shown in FIG. 2 varies from V.sub.h to 0V, the voltage at node A varies from the threshold voltage V.sub.T16 of transistor 16 (which typically is about 0.8 volts) to V.sub.T16 -V.sub.h. The voltage at the V.sub.bb pad is then pumped to a value of V.sub.T16 +V.sub.T14 -V.sub.h, which is higher than the minimum voltage at node A by V.sub.T14, the threshold voltage of transistor 14.
As shown in FIG. 3, in the conventional substrate-bias generator circuit, there is a hidden bipolar transistor 20. This transistor might discharge node A and causes the absolute voltage at the V.sub.bb pad to drop. This effect is more significant for high threshold voltages of transistor 14 when the base-emitter voltage becomes higher, and at high temperature when the turn-on voltage of the base-emitter junction becomes lower and the beta of hidden transistor 20 increases.
By decreasing the threshold voltages of transistors 14 and 16, a more negative voltage can be achieved. This decrease can be implemented by using a non-implanted transistor. Unfortunately, this technique is very risky and unstable because, at low substrate-bias voltages and at high temperature, the non-implanted transistor becomes depleted. It then conducts in both directions, disturbs the pumping action and drops the substrate-bias voltage to a less negative value.